SH7604 Datasheet, PDF (380/633 Pages) Hitachi Semiconductor – Hardware Manual

1
Serial
data
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data _bit bit
D₁
D₇ 0/1 0
TDRE
1
Idle
(mark)
state
FER
RXI interrupt
request generated
1 frame
RXI interrupt
handler reads
data and clears
RDRF bit to 0
ERI interrupt
request generated
by framing error
Figure 13.8 Example of SCI Receive Operation
(8-Bit Data with Parity and One Stop Bit)
13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next, the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13.9 shows an example of communication among processors using the multiprocessor
format.
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