SH7604 Datasheet, PDF (106/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit:
Bit name:
Initial value:
R/W:
15
SCIIP3
0
R/W
14
SCIIP2
0
R/W
13
SCIIP1
0
R/W
12
SCIIP0
0
R/W
11
10
9
8
FRTIP3 FRTIP2 FRTIP1 FRTIP0
0
0
0
0
R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
• Bits 15 to 12—Serial Communication Interface (SCI) Interrupt Priority Level (SCIIP3–
SCIIP0): These bits set the serial communication interface (SCI) interrupt priority level. There
are four bits, so levels 0–15 can be set.
• Bits 11 to 8—Free-Running Timer (FRT) Interrupt Priority Level (FRTIP3–FRTIP0): These
bits set the free-running timer (FRT) interrupt priority level. There are four bits, so levels 0–15
can be set.
• Bits 7 to 0—Reserved: These bits always read 0. The write value should always be 0.
Table 5.5 shows the relationship between on-chip peripheral module interrupts and interrupt
priority level setting registers.
Table 5.5 Interrupt Request Sources and IPRA/IPRB
Register
IPRA
IPRB
Bits 15 to 12
DIVU
SCI
Bits 11 to 8
DMAC0, DMAC1
FRT
Bits 7 to 4
WDT
Reserved
Bits 3 to 0
Reserved
Reserved
As table 5.5 shows, two or three on-chip peripheral modules are assigned to each interrupt priority
register. Set the priority levels by setting the corresponding 4-bit groups (bits 15 to 12, bits 11 to 8,
and bits 7 to 4) with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level
0 (the lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to
the same bits (DMAC0 and DMAC1, or WDT and DRAM refresh control unit), those two
modules have the same priority. A reset initializes IPRA and IPRB to H'0000. They are not
initialized in standby mode.
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