SH7604 Datasheet, PDF (240/633 Pages) Hitachi Semiconductor – Hardware Manual

8.4.6 Cache Initialization
Purges of the entire cache area can only be carried out by writing 0 to the CP bit in CCR. Writing
1 to the CP bit initializes the valid bit of the address array and all bits of the LRU information to 0.
Cache purges are completed in 1 cycle, but additional time is required for writing to CCR. Always
initialize the valid bit and LRU before enabling the cache.
When the cache is enabled, instruction reads are performed from the cache even during writing to
CCR. This means that the prefetched instructions are read from the cache. To do a proper purge,
write 0 to CCR’s CE bit, then disable the cache and purge. Since CCR’s CE bit is cleared to 0 by a
power-on reset or manual reset, the cache can be purged immediately by a reset.
8.4.7 Associative Purges
Associative purges invalidate 1 line (16 bytes) corresponding to specific address contents when
the contents are in the cache. When the contents of shared addresses are rewritten by one CPU in a
multiprocessor configuration, the other CPU cache must be invalidated if it also contains the
address. When writing is performed to the address found by adding H'40000000 to the purged
address, the valid bit of the entry storing the address prior to the addition is initialized to 0. 16
bytes are purged in each write, so a purge of 256 bytes of consecutive areas can be accomplished
in 16 writes. Access sizes when associative purges are performed should be longword. A purge of
1 line requires 2 cycles.
Associative purge:
31 28
Address 010
3
Tag address
19
9
30
Entry
address
—
6
4
Figure 8.9 Associative Purge Access
8.4.8 Data Array Access
The cache data array can be read or written directly via the data array read/write area. The access
sizes for the data array may be byte, word or longword. Data array accesses are completed in 1
cycle for both reads and writes. Since only the cache bus is used, the operation can proceed in
parallel even when another master, such as the DMAC, is using the bus. The data array of way 0 is
mapped on H'C0000000 to H'C00003FF, way 1 on H'C0000400 to H'C00007FF, way 2 on
H'C0000800 to H'C0000BFF and way 3 on H'C0000C00 to H'C0000FFF. When the two-way
mode is being used, the area H'C0000000 to H'C00007FF is accessed as 2 kbytes of on-chip
RAM. When the cache is disabled, the area H'C0000000 to H'C0000FFF can be used as 4 kbytes
of on-chip RAM.
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