SH7604 Datasheet, PDF (616/633 Pages) Hitachi Semiconductor – Hardware Manual

UBC
Break bus cycle register B
(BBRB)
H'FFFFFF68
16/32
Item
Bit Name
Initial Value
R/W
15 14 13 12
————
0000
RRRR
11 10 9
———
000
RRR
Bit
8 7654 32 10
— CPB CPB IDB IDB RWB RWB SZB SZB
1010 10 10
0 0000 00 00
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Value
Description
7, 6 CPU cycle/peripheral 0 0 No channel B user break interrupt generated
cycle select B
(Initial value)
(CPB1, CPB0)
0 1 Break only on CPU cycles
1 0 Break only on peripheral cycles
1 1 Break on both CPU and peripheral cycles
5, 4 Instruction fetch/data 0 0 No channel B user break interrupt generated
access select B
(Initial value)
(IDB1, IDB0)
0 1 Break only on instruction fetch cyclcs
1 0 Break only on data access cycles
1 1 Break on both instruction fetch and data access cycles
3, 2 Read/write select B
0 0 No channel B user break interrupt generated
(RWB1, RWB0)
(Initial value)
0 1 Break only on read cycles
1 0 Break only on write cycles
1 1 Break on both read and write cycles
1, 0 Operand size select B 0 0 Operand size is not a break condition (Initial value)
(SZB1, SZB0)
0 1 Break on byte access
1 0 Break on word access
1 1 Break on longword access
600