SH7604 Datasheet, PDF (119/633 Pages) Hitachi Semiconductor – Hardware Manual

5.7 Usage Notes
1. Do not execute module standby for modules that have the module-stop function when the
possibility remains that an interrupt request may be output.
2. As shown in figure 5.10, the point at which the NMI request is cleared is the state following
the decoding stage for the instruction replaced by the interrupt exception handling.
NMI request
(at fall)
Instruction replaced by
interrupt exception
handling
Start instruction in
NMI routine
FDEEMMEMEE
FDE
NMI request
clearing timing
Figure 5.10 NMI Request Clearing Timing
3. Clearing Interrupt Sources:
External Interrupt Sources: When an interrupt source is cleared by writing to an I/O address,
another instruction will be executed before the write can be completed because of the write
buffer. To ensure that the next instruction is executed after the write is completed, read from
the same address after the write to obtain total synchronization.
• Returning from interrupt handling with an RTE instruction: Figure 5.11 shows how a
minimum interval of 1 cycle is required between the read instruction used for
synchronization and the RTE instruction. A read instruction for synchronization and a
minimum of 1 instruction should thus be executed between the source clear and the RTE
instruction.
• Changing the level during interrupt handling: Figure 5.12 shows how a minimum interval
of 4 cycles is required between the synchronization instruction and the LDC instruction
when an LDC instruction is used to enable another overlapping interrupt by changing the
SR value. A read instruction for synchronization and a minimum of 4 instructions should
thus be executed between the source clear and the LDC instruction.
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