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| SH7604 Datasheet, PDF (553/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
Trr
Trc1
Trc2
Tre
CKIO
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
tCSD1
tRWD
tRSD2
tCASD3
tCASD3
D31âD0
tCSD1
tCASD3
DACKn
WAIT
RAS,
CE
CAS,
OE
CKE
tRASD3
tRASD3
tRASD3
Figure 16.51 DRAM CAS-Before-RAS Refresh Cycle
(TRP = 1 Cycle, TRAS = 2 Cycles, PLL Off)
537
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