SH7604 Datasheet, PDF (266/633 Pages) Hitachi Semiconductor – Hardware Manual

DREQ0
DREQ1
Bus
cycle
CPU
CPU
Channel 0
destination
Channel 0
destination
Channel 1
destination
CPU
Channel 0
source
Channel 0
source
Channel 1
source
Figure 9.3 Fixed Mode Burst DMA Transfer (Dual Address, Active-Low DREQ Level)
In cycle-steal mode, once a channel 0 request is accepted, channel 1 requests are also accepted
until the next request is made, which makes more effective use of the bus cycle. When requests
come simultaneously for channel 0 and channel 1 when DMA operation is starting, the first is
transmitted multiplexed with channel 0 and thereafter channel 1 and channel 0 transfers are
performed alternately.
DREQ0
DREQ1
Bus
cycle
CPU
CPU
Channel 0
source
Channel 1
source
Channel 0
source
CPU
CPU
CPU
Channel 0
destination
Channel 1
destination
Figure 9.4 Fixed Mode Cycle-Steal DMA Transfer
(Dual Address, Active-Low DREQ Level)
Round-Robin Mode: Switches the priority of channel 0 and channel 1, shifting their ability to
receive transfer requests. Each time one transfer ends on one channel, the priority shifts to the
other channel. The channel on which the transfer just finished is assigned low priority. After reset,
channel 0 has higher priority than channel 1.
Figure 9.5 shows how the priority changes when channel 0 and channel 1 transfers are requested
simultaneously and another channel 0 transfer is requested after the first two transfers end. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 1 and 0.
2. Channel 1 has the higher priority, so the channel 1 transfer begins first (channel 0 waits for
transfer).
3. When the channel 1 transfer ends, channel 1 becomes the lower-priority channel.
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