SH7604 Datasheet, PDF (88/633 Pages) Hitachi Semiconductor – Hardware Manual

4.3.2 Address Error Exception Handling
When an address error occurs, address error exception handling begins after the end of the bus
cycle in which the error occurred and completion of the executing instruction. The CPU operates
as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last instruction executed .
3. The exception service routine start address is fetched from the exception vector table entry that
corresponds to the address error that occurred, and the program starts executing from that
address. The jump that occurs is not a delayed branch.
4.4 Interrupts
4.4.1 Interrupt Sources
Table 4.7 shows the sources that initiate interrupt exception handling. These are divided into NMI,
user breaks, IRL, and on-chip peripheral modules. Each interrupt source is allocated a different
vector number and vector table address offset. See table 5.4, Interrupt Exception Vectors and
Priority Order, in section 5, Interrupt Controller, for more information.
Table 4.7 Types of Interrupt Sources
Type
NMI
User break
IRL
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller
IRL1–IRL15 (external input)
Direct memory access controller (DMAC)
Division unit (DIVU)
Serial communication interface (SCI)
Free-running timer (FRT)
Watchdog timer (WDT)
Bus state controller (BSC)
Number of Sources
1
1
15
2
1
4
3
1
1
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