SH7604 Datasheet, PDF (258/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bits 7 to 0—Vector Number Bits 7–0 (VC7–VC0): Set the interrupt vector numbers at the end
of a DMAC transfer. Interrupt vector numbers of 0–127 can be set. When a transfer-end
interrupt occurs, exception handling and interrupt control fetch the vector number and control
is transferred to the specified interrupt handling routine. The VC7–VC0 bits are undefined
upon reset and in standby mode. Always write 0 to VC7.
9.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1) are 8-bit read/write
registers that set the vector address of the DMAC transfer request source. They are written as 8-bit
values. They are initialized to H'00 by a reset, but retain their values in a module standby.
• Bits 7 to 2—Reserved
• Bits 1 and 0—Resource Select Bits 1 and 0 (RS1, RS0): Specify which transfer request to input
to the DMAC. Changing the transfer request source must be done when the DMA enable bit
(DE) is 0. The RS1 and RS0 bits are initialized to 00 by a reset.
Bit 1: RS1
Bit 0: RS0
Description
0
0
DREQ (external request)
(Initial value)
0
1
RXI (on-chip SCI receive-data-full interrupt transfer request)*
1
0
TXI (on-chip SCI transmit-data-empty interrupt transfer
request)*
1
1
Reserved (setting prohibited)
Note: For RX2 and TX1, set for dual transfer mode.
The DREQ settings in CHCR are DS = 1 and DL = 0.
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