SH7604 Datasheet, PDF (300/633 Pages) Hitachi Semiconductor – Hardware Manual

• The DMA master enable (DME) bit in DMAOR is cleared to 0.
Clearing the DME bit in DMAOR forcibly aborts the transfers on both channels at the end of
the current bus cycle. When the transfer is the final transfer, TE = 1 and the transfer ends.
9.4 Examples of Use
9.4.1 DMA Transfer Between On-Chip SCI and External Memory
In the following example, data received on the on-chip serial communication interface (SCI) is
transferred to external memory using DMAC channel 1. Table 9.9 shows the transfer conditions
and register settings.
Table 9.9 Register Settings for Transfers between On-Chip SCI and External Memory
Transfer Conditions
Register Setting
Transfer source: RDR of on-chip SCI
SAR1
H'FFFFFE05
Transfer destination: external memory (word space)
DAR1
Destination address
Number of transfers: 64
TCR1
H'0040
Transfer destination address: incremented
CHCR1 H'4045
Transfer source address: fixed
Bus mode: cycle-steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (DE = 1)
Channel priority: Fixed (0 > 1) (DME = 1)
DMAOR H'0001
Transfer request source (transfer request signal): SCI (RXI) DRCR1 H'01
Note: Check the CPU interrupt level when interrupts are enabled in the SCI.
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