SH7604 Datasheet, PDF (149/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 7.1 Pin Configuration (cont)
Signal
With Bus
I/O Released Description
CASLH, O Hi-Z
DQMLU,
WE1
When DRAM is used, connected to CAS pin for the third byte
(D15–D8). When synchronous DRAM is used, connected to DQM
pin for the third byte. When pseudo-SRAM is used, connected to
WE pin for the third byte. For basic interface, indicates writing to
the third byte.
CASLL, O Hi-Z
DQMLL,
WE0
When DRAM is used, connected to CAS pin for the least significant
byte (D7–D0). When synchronous DRAM is used, connected to
DQM pin for the least significant byte. When pseudo-SRAM is
used, connected to WE pin for the least significant byte. For basic
interface, indicates writing to the least significant byte.
RD
O Hi-Z
Read pulse signal (read data output enable signal). Normally,
connected to the device’s /OE pin; when there is an external data
buffer, the read cycle data can only be output when this signal is
low.
WAIT
I Ignore
Hardware wait input.
BACK, I I
BRLS
Bus use enable input in partial-share master or slave mode: BACK.
Bus release request input in total master: BRLS.
BREQ, O O
BGR
Bus request output in partial-share master or slave mode: BREQ.
Bus grant output in total master: BGR.
CKE
OO
Synchronous DRAM clock enable control. Signal for supporting
synchronous DRAM self-refresh.
IVECF O Hi-Z
Interrupt vector fetch.
DREQ0 I I
DMA request 0.
DACK0 O O
DMA acknowledge 0.
DREQ1 I I
DMA request 1.
DACK1 O O
DMA acknowledge 1.
Note: Hi-Z: High impedance
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