SH7604 Datasheet, PDF (526/633 Pages) Hitachi Semiconductor – Hardware Manual

CKIO
Upper
address
Lower
address
BS
CSn
T_C
T_W
T_d1
T_d2
T_d3
T_d4
RD/WR
WE
RD
WEn
CASxx
DQMxx
D31–D0
t_DQMD
DACKn
WAIT
RAS
CE
CAS
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.24 Synchronous DRAM Read Bus Cycle
(Bank Active, Same Row Access, CAS Latency = 2 Cycles)
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