SH7604 Datasheet, PDF (182/633 Pages) Hitachi Semiconductor – Hardware Manual

Tr
Tc
Trwl
Tap
CKIO
A26–A11
A10
A9–A1
CS2 or
CS3
RAS
CAS
WE
DQMxx
D31–D0
BS
Figure 7.18 Basic Write Cycle Timing (Auto-Precharge)
7.5.6 Bank Active Function
A synchronous DRAM bank function is used to support high-speed accesses of the same row
address. When the RASD bit in MCR is set to 1, read/write accesses are performed using
commands without auto-precharge (READ, WRIT). In this case, even when the access is
completed, no precharge is performed. When accessing the same row address in the same bank, a
READ or WRIT command can be called immediately without calling an ACTV command, just
like the RAS down mode of the DRAM’s high-speed page mode. Synchronous DRAM is divided
into two banks, so one row address in each can stay active. When the next access is to a different
row address, a PRE command is called first to precharge the bank, and access is performed by an
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