SH7604 Datasheet, PDF (3/633 Pages) Hitachi Semiconductor – Hardware Manual

Preface
The SH7604 implements high-performance operations by using a CPU which employs the
Reduced Instruction Set Computer (RISC) system. The SH7604 is a new-generation RISC
microcomputer which realizes low power consumption, an essential feature of microcomputer
devices, as well as integrating peripheral features necessary for system configuration.
The CPU of the SH7604 has a set of RISC-type instructions; basic instructions operate at one state
per instruction, that is, in one system clock cycle, dramatically increasing execution speeds. The
SH7604 incorporates a 32-bit multiplier which performs high-speed sum-of-product (multiply-
and-accumulate) operations. Instructions used by the SH7604 are upwardly compatible with the
SH7000 Series, allowing easy migration from the SH7000 Series to the SH7604.
Moreover, the SH7604 incorporates on-chip peripheral modules such as an interrupt controller
(INTC), direct memory access controller (DMAC), division unit (DIVU), timers (FRT, WDT),
and serial communication interface (SCI), so that a user system can be configured using the
minimum number of parts.
On-chip cache memory enhances the CPU throughput. A bus control feature, which supports
external memory access, improves external memory access efficiency, allowing direct connection
to synchronous DRAM, DRAM, and pseudo-SRAM without the help of glue logic.
This hardware manual explains the hardware features of the SH7604. For details of instructions,
see the Programming Manual.
Related Documents
SH7604 instructions
“SH-1/SH-2 Programming Manual” (Document No.: ADE-602-063B)
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