SH7604 Datasheet, PDF (227/633 Pages) Hitachi Semiconductor – Hardware Manual

When the CPU starts a read access to a cache area, it first takes a cycle to find the cache. If there is
data in the cache, it fetches it and completes the access. If there is no data in the cache, a cache
data fill is performed via the internal bus, so four consecutive longword reads occur. For misses
that occur when byte or word operands are accessed or branches occur to odd word boundaries (4n
+ 2 addresses), filling is always performed by longword accesses on the chip-external interface. In
the cache-through area, the access is to the actual access address. When the access is an instruction
fetch, the access size is always longword.
For cache-through areas and on-chip peripheral module read cycles, after an extra cycle is added
to determine the cycle, the read cycle is started through the internal bus. Read data is sent to the
CPU through the cache bus.
When word write cycles access the cache area, the cache is searched. When the data of the
relevant address is found, it is written here. In parallel to this, the actual writing occurs through the
internal bus. When the right to use the internal bus is held, the CPU is notified that the write is
completed without waiting for the actual writing to the on-chip peripheral module or off the chip
to end. When the right to use the internal bus is not held, as when it is being used by the DMAC or
the like, there is a wait until the bus is acquired before the CPU is notified of completion.
Accesses to cache-through areas and on-chip peripheral modules work the same as in the cache
area, except for the cache search and write.
Because the bus state controller has one level of write buffer, the internal bus can be used for
another access even when the chip-external bus cycle has not ended. After a write has been
performed to low-speed memory off the chip, performing a read or write with an on-chip
peripheral module enables an access to the on-chip peripheral module without having to wait for
the completion of the write to low-speed memory.
During reads, the CPU always has to wait for the end of the operation. To immediately continue
processing after checking that the write to the device of actual data has ended, perform a dummy
read access to the same address consecutively to check that the write has ended.
The bus state controller’s write buffer functions in the same way during accesses from the DMAC.
A dual-address DMA transfer thus starts in the next read cycle without waiting for the end of the
write cycle. When both the source address and destination address of the DMA are external spaces
to the chip, however, it must wait until the completion of the previous write cycle before starting
the next read cycle.
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