SH7604 Datasheet, PDF (278/633 Pages) Hitachi Semiconductor – Hardware Manual

Clock
DACK
Address
bus
Row Column
address address
DMAC write (basic timing)
Figure 9.21 DACK Output in Synchronous DRAM Write
(Auto-Precharge, AM = 1)
When external memory is set as bank active synchronous DRAM, during a burst read the
acknowledge signal is output across the read command, wait and read address when the row
address is the same as the previous address output (figure 9.22). When the row address is different
from the previous address, the acknowledge signal is output across the precharge, row address,
read command, wait and read address (figure 9.23).
Clock
DACK
Address
bus
CPU
Read
command
Read 1
Read 2 Read 3 Read 4
DMAC read (basic timing)
Figure 9.22 DACK Output in Synchronous DRAM Burst Read
(Bank Active, Same Row Address, AM = 0)
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