SH7604 Datasheet, PDF (91/633 Pages) Hitachi Semiconductor – Hardware Manual

1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
3. The exception service routine start address is fetched from the exception vector table entry that
corresponds to the exception that occurred. That address is jumped to and the program starts
executing. The jump that occurs is not a delayed branch.
4.5.4 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU
handles general illegal instructions in the same way as illegal slot instructions. Unlike processing
of illegal slot instructions, however, the program counter value stored is the start address of the
undefined code.
4.6 When Exception Sources are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not immediately accepted but is stored instead, as described in
table 4.10. When this happens, it will be accepted when an instruction for which exception
acceptance is possible is decoded.
Table 4.10 Exception Source Generation Immediately after a Delayed Branch Instruction
or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence
Address Error
Interrupt
Immediately after a delayed branch instruction^*1
Not accepted
Not accepted
Immediately after an interrupt-disabled instruction^*2
Accepted
Not accepted
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
4.6.1 Immediately after a Delayed Branch Instruction
When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded,
neither address errors nor interrupts are accepted. The delayed branch instruction and the
instruction located immediately after it (delay slot) are always executed consecutively, so no
exception handling occurs between the two.
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