SH7604 Datasheet, PDF (137/633 Pages) Hitachi Semiconductor – Hardware Manual

3. An instruction set for a break before execution breaks when it is confirmed that the instruction
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delayed branch instruction
or an instruction following an interrupt-disabled instruction, such as LDC, the interrupt is
generated prior to execution of the first instruction at which the interrupt is subsequently then
accepted.
4. When the condition stipulates after execution, the instruction set with the break condition is
executed and then the interrupt is generated prior to the execution of the next instruction. As
with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind
of break is set for a delayed branch instruction or an interrupt-disabled instruction, such as
LDC, the interrupt is generated at the first instruction at which the interrupt is subsequently
accepted.
5. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
There is thus no need to set break data for an instruction fetch cycle break.
6.3.3 Break on Data Access Cycle
1. The memory cycles in which CPU data access breaks occur are: memory cycles from
instructions, and stacking and vector reads during exception handling. These breaks cannot be
used in dummy cycles for single reads of synchronous DRAM.
2. The relationship between the data access cycle address and the comparison condition for
operand size are shown in table 6.3. This means that when address H'00001003 is set without
specifying the size condition, for example, the bus cycle in which the break condition is
satisfied is as follows (where other conditions are met):
Longword access at address H'00001000
Word access at address H'00001002
Byte access at address H'00001003
Table 6.3 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Longword
Word
Byte
Address Compared
Break address register bits 31–2 compared with address bus bits 31–2
Break address register bits 31–1 compared with address bus bits 31–1
Break address register bits 31–0 compared with address bus bits 31–0
3. When the data value is included in the break conditions on channel B:
When the data value is included in the break conditions, specify either longword, word, or byte
as the operand size in the break bus cycle registers (BBRA, BBRB). When data values are
included in break conditions, a break interrupt is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in the two
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