SH7604 Datasheet, PDF (305/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 10.1 Division Unit Register Configuration
Register
Abbr. R/W Initial Value Address
Access Size^*1
Divisor register
DVSR R/W Undefined H'FFFFFF00 32
Dividend register L for 32-bit
division
DVDNT R/W Undefined H'FFFFFF04 32
Division control register
DVCR R/W H'00000000 H'FFFFFF08 16, 32
Vector number setting register VCRDIV R/W Undefined^*2 H'FFFFFF0C 16, 32
DIV
Dividend register H
DVDNTH R/W Undefined H'FFFFFF10 32
Dividend register L
DVDNTL R/W Undefined H'FFFFFF14 32
Notes: 1. Accesses to the division unit are read and written in 32-bit units. DVCR and VCRDIV
permit 16 and 32-bit accesses. When registers other than CONT and VCRDIV are
accessed with word accesses, undefined values are read or written.
2. The initial value of VCRDIV is H'0000**** (asterisks represent undefined values).
10.2 Description of Registers
10.2.1 Divisor Register (DVSR)
Bit: 31
30
29
…
3
2
1
0
Bit name:
…
Initial value: —
—
—
…
—
—
—
—
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
The divisor register (DVSR) is a 32-bit read/write register in which the divisor for the operation is
written. It is not initialized by a power-on reset or manual reset, in standby mode, or during
module standbys.
10.2.2 Dividend Register L for 32-Bit Division (DVDNT)
Bit: 31
30
29
…
3
2
1
0
Bit name:
…
Initial value: —
—
—
…
—
—
—
—
R/W: R/W R/W R/W
…
R/W R/W R/W R/W
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