SH7604 Datasheet, PDF (18/633 Pages) Hitachi Semiconductor – Hardware Manual

• On-chip multiplier: multiply operations (32 bits × 32 bits → 64 bits) and multiply-and-
accumulate operations (32 bits × 32 bits + 64 bits → 64 bits) executed in 2 to 4 states
• Five-stage pipeline
Operating Modes:
• Clock mode: selected from the combination of an on-chip oscillator module, a frequency
multiplier, clock output, PLL synchronization, and 90° phase shifting (the range of choices
depends on the package)
• Slave/master mode
• Processing states
 Power-on reset state
 Manual reset state
 Exception handling state
 Program execution state
 Power-down state
 Bus-released state
• Power-down states
 Sleep mode
 Standby mode
 Module stop mode
Interrupt Controller (INTC):
• Five external interrupt pins (NMI, IRL0 to IRL3), encoded input of 15 external interrupt
sources via pins IRL0 to IRL3
• Twelve internal interrupt sources (DMAC × 2, DIVU × 1, FRT × 3, WDT × 1, SCI × 4,
REF × 1)
• Sixteen programmable priority levels
• Vector number settable for each internal interrupt source
• Auto-vector or external vector selectable as vector for external interrupts via pins IRL0 to
IRL3
User Break Controller (UBC):
• Generates an interrupt when the CPU or DMAC generates an address, data, or bus cycle with
the specified conditions (address, data, CPU cycle/non-CUP cycle, instruction fetch/data
access, read/write, byte/word/longword access)
• Simplifies configuration of a self-debugger
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