SH7604 Datasheet, PDF (51/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 2.13 Arithmetic Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC
Rm,Rn
ADDV
Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PZ Rn
CMP/PL Rn
CMP/ST Rm,Rn
DIV1
DIV0S
Rm,Rn
Rm,Rn
DIV0U
DMULS.
Rm,Rn
Instruction Code
Operation
0011nnnnmmmm1100 Rn + Rm → Rn
0111nnnniiiiiiii Rn + imm → Rn
0011nnnnmmmm1110 Rn + Rm + T → Rn,
Carry → T
0011nnnnmmmm1111 Rn + Rm → Rn,
Overflow → T
10001000iiiiiiii If R0 = imm, 1 → T
Execution
States
1
1
1
1
1
0011nnnnmmmm0000 If Rn = Rm, 1 → T 1
0011nnnnmmmm0010 If Rn≥Rm with
1
unsigned data, 1 → T
0011nnnnmmmm0011 If Rn ≥ Rm with
1
signed data, 1 → T
0011nnnnmmmm0110 If Rn > Rm with
1
unsigned data, 1 → T
0011nnnnmmmm0111 If Rn > Rm with
1
signed data, 1 → T
0100nnnn00010001 If Rn ≥ 0, 1 → T
1
0100nnnn00010101 If Rn > 0, 1 → T
1
0010nnnnmmmm1100 If Rn and Rm have
an equivalent byte,
1→T
0011nnnnmmmm0100 Single-step division
(Rn ÷ Rm)
0010nnnnmmmm0111 MSB of Rn → Q,
MSB of Rm → M,
M^Q→T
0000000000011001 0 → M/Q/T
0011nnnnmmmm1101
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64
bits
1
1
1
1
2 to 4^*
T Bit
—
—
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
—
35