SH7604 Datasheet, PDF (419/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 15.5 Control Signal Timing (Conditions: V_CC = 5.0 V ± 10%, Ta = –20 to +75°C)
(cont)
Item
Symbol Min
Max
Unit Figure
BREQ delay time 1 (PLL on)
BACK setup time 1 (PLL on)
BACK hold time 1 (PLL on)
BREQ delay time 1 (PLL on, 1/4 cycle delay)
BACK setup time 1 (PLL on, 1/4 cycle delay)
BACK hold time 1 (PLL on, 1/4 cycle delay)
BREQ delay time 2 (PLL off)
BACK setup time 2 (PLL off)
BACK hold time 2 (PLL off)
Bus tri-state delay time 1 (PLL on)
Bus buffer on time 1 (PLL on)
Bus tri-state delay time 1 (PLL on, 1/4 cycle
delay)
t_BRQD1
t_BAKS1
t_BAKH1
t_BRQD1
t_BAKS1
t_BAKH1
t_BRQD2
t_BAKS2
t_BAKH2
t_BOFF1
t_BON1
t_BOFF1
—
1/2 tcyc + 18 ns
1/2 tcyc + 9 —
ns
9 – 1/2 tcyc —
ns
—
3/4 tcyc + 18 ns
1/4 tcyc + 9 —
ns
9 – 1/4 tcyc —
ns
—
28
ns
9
—
ns
19
—
ns
0
25
ns
0
18
ns
1/4 tcyc 1/4 tcyc + 25 ns
15.12
15.12
15.13
15.10,
15.12
15.10,
15.12
Bus buffer on time 1 (PLL on, 1/4 cycle delay) t_BON1
Bus tri-state delay time 1 (PLL off)
t_BOFF1
Bus buffer on time 1 (PLL off)
t_BON1
Bus tri-state delay time 2 (PLL on)
t_BOFF2
Bus buffer on time 2 (PLL on)
t_BON2
Bus tri-state delay time 2 (PLL on, 1/4 cycle t_BOFF2
delay)
Bus buffer on time 2 (PLL on, 1/4 cycle delay) t_BON2
Bus tri-state delay time 3 (PLL off)
t_BOFF3
Bus buffer on time 3 (PLL off)
t_BON3
1/4 tcyc
0
0
1/2 tcyc
1/2 tcyc
3/4 tcyc
3/4 tcyc
0
0
1/4 tcyc + 18 ns
30
ns
25
ns
1/2 tcyc + 25 ns
1/2 tcyc + 18 ns
3/4 tcyc + 25 ns
15.11,
15.13
15.10,
15.12
15.10,
3/4 tcyc + 18 ns
30
ns
25
ns
15.12
15.11,
15.13
403