SH7604 Datasheet, PDF (138/633 Pages) Hitachi Semiconductor – Hardware Manual

bytes at bits 15–8 and bits 7–0 of the break data register B (BDRB) and break data mask
register B (BDMRB). When word or byte is set, bits 31–16 of BDRB and BDMRB are
ignored.
6.3.4 Break on External Bus Cycle
1. Enable the external bus break enable bit (the EBBE bit in BRCR) to generate a break for a bus
cycle generated by the external bus master when the bus is released. External bus cycle breaks
can be used in total master mode or total slave mode.
2. Address and read/write can be set for external buses, but size cannot be specified. Setting sizes
of byte/word/longword will be ignored. Also, no distinction can be made between instruction
fetch and data access for external bus cycles. All cycles are considered data access cycles, so
set 1 in bits IDA1 and IDB1 in BBRA and BBRB.
3. External input of addresses uses A26–A0, so set bits 31–27 of the break address registers
(BARA, BARB) to 0, or set bits 31–27 of the break address mask registers (BAMRA,
BAMRB) to 1 to mask the addresses not input.
4. When the conditions set for the external bus cycle are satisfied, the CMFPA and CMFPB bits
are set for the respective channels.
6.3.5 Program Counter (PC) Values Saved
1. Break on Instruction Fetch (Before Execution): The program counter (PC) value saved to the
stack in user break interrupt exception handling is the address that matches the break condition.
The user break interrupt is generated before the fetched instruction is executed. If a break
condition is set on an instruction that follows an interrupt-disabled instruction, however, the
break occurs before execution of the instruction at which the next interrupt is accepted, so the
PC value saved is the address of the break.
2. Break on Instruction Fetch (After Execution): The program counter (PC) value saved to the
stack in user break interrupt exception handling is the address executed after the one that
matches the break condition. The fetched instruction is executed and the user break interrupt
generated before the next instruction is executed. If a break condition is set on an interrupt-
disabled instruction, the break occurs before execution of the instruction at which the next
interrupt is accepted, so the PC value saved is the address of the break.
3. Break on Data Access (CPU/Peripheral): The program counter (PC) value is the start address
of the next instruction after the last instruction executed before the user break exception
handling started. When data access (CPU/peripheral) is set as a break condition, the place
where the break will occur cannot be specified exactly. The break will occur at an instruction
fetched close to where the data access that is to receive the break occurs.
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