SH7604 Datasheet, PDF (65/633 Pages) Hitachi Semiconductor – Hardware Manual

Section 3 Oscillator Circuits and Operating Modes
3.1 Overview
Operation of the on-chip clock pulse generator, CS0 area bus width specification, and switching
between master and slave modes are controlled by the operating mode pins. A crystal resonator or
external clock can be selected as the clock source.
3.2 On-Chip Clock Pulse Generator and Operating Modes
3.2.1 Clock Pulse Generator
A block diagram of the on-chip clock pulse generator circuit is shown in figure 3.1.
CAP1
CKIO
PLL circuit 1
Standby
control signal
Clock
CAP2
EXTAL
XTAL
CKPREQ/
CKM
Oscillator PLL circuit 2
Clock mode pins
MD2
MD1
MD0
CKPACK*
Clock mode
control circuit
Note: See section 14.4.4, Clock Pause Function
Figure 3.1 Block Diagram of Clock Pulse Generator Circuit
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