SH7604 Datasheet, PDF (405/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 0: MSTP0
0
1
Description
SCI running
Clock supply to SCI halted
(Initial value)
14.3 Sleep Mode
14.3.1 Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit in SBYCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to run in sleep mode.
14.3.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset.
Cancellation by an Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt
exception handling is executed. Sleep mode is not canceled if the interrupt cannot be accepted
because its priority level is equal to or less than the mask level set in the CPU’s status register
(SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module.
Cancellation by a DMA Address Error: If a DMA address error occurs, sleep mode is canceled
and DMA address error exception handling is executed.
Cancellation by a Power-On Reset: A power-on reset cancels sleep mode.
Cancellation by a Manual Reset: A manual reset cancels sleep mode.
14.4 Standby Mode
14.4.1 Transition to Standby Mode
To enter standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction. The
chip switches from the program execution state to standby mode. The NMI interrupt cannot be
accepted when the SLEEP instruction is executed, or for the following five cycles. In standby
mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-
chip peripheral modules as well. CPU register contents are held, and some on-chip peripheral
modules are initialized.
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