SH7604 Datasheet, PDF (358/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 1: Bit 0:
CKE1 CKE0 Description
0
0
Asynchronous mode
Internal clock, SCK pin used for input pin (input signal
is ignored or output pin output level is undefined)^*1
Clocked synchronous mode Internal clock, SCK pin used for synchronous clock
output*¹
0
1
Asynchronous mode
Internal clock, SCK pin used for clock output*²
Clocked synchronous mode Internal clock, SCK pin used for synchronous clock
output
1
0
Asynchronous mode
External clock, SCK pin used for clock input*³
Clocked synchronous mode External clock, SCK pin used for synchronous clock
input
1
1
Asynchronous mode
External clock, SCK pin used for clock input*³
Clocked synchronous mode External clock, SCK pin used for synchronous clock
input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
13.2.7 Serial Status Register (SSR)
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate the SCI operating status.
The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is
initialized to H'84 by a reset and in standby and module standby mode.
Bit: 7
6
5
4
3
Bit name: TDRE RDRF ORER FER PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
• Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR into TSR and new serial transmit data can be written in TDR.
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