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| SH7604 Datasheet, PDF (559/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
Tr
Tc1
CKIO
Tc2
Tc1
Tc2
Upper
address
Lower
address
BS
tAD
tBSD
tBSD
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
tWED1
tWED1
tWDD
tWDH1
tDACD2 tDACD1
WAIT
RAS,
CE
CAS,
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.57 Pseudo-SRAM Write Cycle
(Static Column Mode, PLL On, TRP = 1 Cycle, RCD = 1 Cycle, No Waits)
543
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