SH7604 Datasheet, PDF (154/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 5: A0LW1
0
1
Bit 4: A0LW0
0
1
0
1
Description
3 waits
4 waits
5 waits
6 waits
(Initial value)
• Bits 2 to 0—Enable for DRAM and Other Memory (DRAM2–DRAM0)
DRAM2 DRAM1 DRAM0 Description
0
0
0
Areas 2 and 3 are ordinary spaces
(Initial value)
1
Area 2 is ordinary space; area 3 is synchronous DRAM space
1
0
Area 2 is ordinary space; area 3 is DRAM space
1
Area 2 is ordinary space; area 3 is pseudo-SRAM space
1
0
0
Area 2 is synchronous DRAM space, area 3 is ordinary space
1
Areas 2 and 3 are synchronous DRAM spaces
1
0
Reserved (do not set)
1
Reserved (do not set)
7.2.2 Bus Control Register 2 (BCR2)
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 —
—
Initial value: 1
1
1
1
1
1
0
0
R/W: R/W R/W R/W R/W R/W R/W
R
R
Initialize BCR2 after a power-on reset and do not write to it thereafter. When writing to it, write
the same values as those the bits are initialized to. Do not access any space other than CS0 until
the register initialization ends.
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