SH7604 Datasheet, PDF (324/633 Pages) Hitachi Semiconductor – Hardware Manual

11.4.2 Output Timing for Output Compare
When a compare match occurs, the output level set in the OLVL bit in TOCR is output from the
output compare output pins (FTOA, FTOB). Figure 11.6 shows the timing for output of output
compare A.
Timer drive
clock
FRC
N
N+1
N
N+1
OCRA
N
N
Compare
match A
signal
OLVLA
Output
compare A
output pin
FTOA
Clear*
Note: ↓ Indicates instruction execution by software
Figure 11.6 Output Timing for Output Compare A
11.4.3 FRC Clear Timing
FRC can be cleared on compare match A. Figure 11.7 shows the timing.
Timer drive
clock
Compare
match A
signal
FRC
N
H'0000
Figure 11.7 Compare Match A Clear Timing
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