SH7604 Datasheet, PDF (623/633 Pages) Hitachi Semiconductor – Hardware Manual

BSC
Bus control register 1 (BCR1)
H'FFFFFFE0
16/32
Bit
Item
15 14 13 12 11 10 9 8 7 6 5 4 3 2
10
Bit Name MAS
END BST PSHR AHLW AHLW A1LW A1LW A0LW A0LW
DRAM DRAM DRAM
TER — — IAN ROM
1
0
1
0
1
0— 2
1
0
Initial Value — 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0
R/W
R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Bit
15
12
11
10
9, 8
7, 6
5, 4
2 to 0
Bit Name
Value
Description
Bus arbitration
0 Master mode
(MASTER)
1 Slave mode
Endian specification for
0 Big-endian, as in other areas (Initial value)
area 2 (ENDIAN)
1 Little-endian
Area 0 burst ROM
0 Area 0 is accessed normally (Initial value)
enable (BSTROM)
1 Area 0 is accessed as burst ROM
Partial space share
0 Total master mode when MD5 = 0 (Initial mode)
specification (PSHR)
1 Partial-share master mode when MD5 = 0
Long wait specification 0 0 3 waits (Initial value)
for areas 2 and 3
0 1 4 waits
(AHLW1, AHLW0)
1 0 5 waits
1 1 6 waits
Long wait specification 0 0 3 waits (Initial value)
for area 1 (A1LW1,
0 1 4 waits
A1LW0)
1 0 5 waits
1 1 6 waits
Long wait specification 0 0 3 waits (Initial value)
for area 0 (A0LW1,
0 1 4 waits
A0LW0)
1 0 5 waits
1 1 6 waits
Enable for DRAM and 0 0 0 Areas 2 and 3 are ordinary spaces (Initial value)
other memory (DRAM2– 0 0 1 Area 2 is ordinary space; area 3 is synchronous
DRAM0)
DRAM space
0 1 0 Area 2 is ordinary space; area 3 is DRAM space
0 1 1 Area 2 is ordinary space; area 3 is pseudo-SRAM
space
1 0 0 Area 2 is synchronous DRAM space; area 3 is
ordinary space
1 0 1 Areas 2 and 3 are synchronous DRAM spaces
1 1 0 Reserved (setting prohibited)
1 1 1 Reserved (setting prohibited)
607