SH7604 Datasheet, PDF (134/633 Pages) Hitachi Semiconductor – Hardware Manual

• Bit 12—UBC Mode (UMD): Selects SH7000 series-compatible mode or SH7604 mode.
Bit 12: UMD
0
1
Description
Compatible mode for SH7000 Series UBCs
SH7604 mode
(Initial value)
• Bit 11—Reserved: This bit always reads 0. The write value should always be 0.
• Bit 10—PC Break Select A (PCBA): Selects whether to place the channel A break in the
instruction fetch cycle before or after instruction execution.
Bit 10: PCBA
0
1
Description
Places the channel A instruction fetch cycle break before instruction
execution
(Initial value)
Places the channel A instruction fetch cycle break after instruction
execution
• Bits 9 and 8—Reserved: These bits always read 0. The write value should always be 0.
• Bit 7—CPU Condition-Match Flag B (CMFCB): Set to 1 when CPU bus cycle conditions
included in the break conditions set for channel B are met. Not cleared to 0 (once set, it must
be cleared by a write before it can be used again).
Bit 7: CMFCB
0
1
Description
Channel B CPU cycle conditions do not match, no user break interrupt
generated
(Initial value)
Channel B CPU cycle conditions have matched, user break interrupt
generated
• Bit 6—Peripheral Condition-Match Flag B (CMFPB): Set to 1 when peripheral bus cycle
conditions (on-chip DMAC, or external bus cycle when external bus monitoring is enabled)
included in the break conditions set for channel B are met. Not cleared to 0 (once set, it must
be cleared by a write before it can be used again).
Bit 6: CMFPB
0
1
Description
Channel B peripheral cycle conditions do not match, no user break
interrupt generated
(Initial value)
Channel B peripheral cycle conditions have matched, user break
interrupt generated
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