SH7604 Datasheet, PDF (123/633 Pages) Hitachi Semiconductor – Hardware Manual

Section 6 User Break Controller
6.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. Break
conditions are set in the UBC and a user break interrupt is generated according to the conditions of
the bus cycle generated by the CPU, on-chip DMAC, or external bus master.
This function makes it easy to design an effective self-monitoring debugger, enabling the chip to
debug programs without using an in-circuit emulator. The UBC can be set in an SH7000 series
compatible mode, facilitating porting of monitoring programs that use other SH7000 series UBCs.
6.1.1 Features
The features of the user break controller are listed below:
• The following break compare conditions can be set: Two break channels (channel A, channel
B). User break interrupts can be requested using either independent or sequential condition for
the two channels (sequential breaks are channel A, then channel B).
 Address
 Data (channel B only)
 Bus master: CPU cycle/DMA cycle/external bus cycle
 Bus cycle: instruction fetch/data access
 Read or write
 Operand size: byte/word/longword
• User break interrupt generated upon satisfying break conditions. A user-designed user break
interrupt exception handling routine can be run.
• Select breaking in the instruction fetch cycle before the instruction is executed, or after.
• Compatible with SH7000 series UBCs after a power-on reset.
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