SH7604 Datasheet, PDF (56/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 2.17 System Control Instructions
Instruction
Instruction Code
CLRT
0000000000001000
CLRMAC
0000000000101000
LDC Rm,SR
0100mmmm00001110
LDC Rm,GBR
0100mmmm00011110
LDC Rm,VBR
0100mmmm00101110
LDC.L @Rm+,SR 0100mmmm00000111
LDC.L @Rm+,GBR 0100mmmm00010111
LDC.L @Rm+,VBR 0100mmmm00100111
LDS Rm,MACH 0100mmmm00001010
LDS Rm,MACL 0100mmmm00011010
LDS Rm,PR
0100mmmm00101010
LDS.L @Rm+,MACH 0100mmmm00000110
LDS.L @Rm+,MACL 0100mmmm00010110
LDS.L @Rm+,PR 0100mmmm00100110
NOP
0000000000001001
RTE
0000000000101011
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
Operation
0→T
0 → MACH, MACL
Rm → SR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm
(Rm) → MACL, Rm + 4 → Rm
(Rm) → PR, Rm + 4 → Rm
No operation
Delayed branch, stack area →
PC/SR
1→T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Execu-
tion
T
States Bit
1
0
1
—
1
LSB
1
—
1
—
3
LSB
3
—
3
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
4
—
1
1
3^*
—
1
—
1
—
1
—
2
—
2
—
2
—
40