SH7604 Datasheet, PDF (203/633 Pages) Hitachi Semiconductor – Hardware Manual

The SH7604 has an address comparator to detect matches of row addresses in burst mode. When
this function is used and the BE bit in MCR is set to 1, setting the MCR’s RASD bit (which
specifies RAS down mode) to 1 places the SH7604 in RAS down mode, which leaves the RAS
signal asserted. Since the CASHH, CASHL, CASLH and CASLL signals are shared with WE3,
WE2, WE1 and WE0 of ordinary space, however, write cycles to ordinary space during RAS
down mode will simultaneously initiate an erroneous write access to the DRAM. This means that
when no external devices that write to other than DRAM are connected, a DRAM can be directly
interfaced using RAS down mode. When RAS down mode is used, the refresh cycle must be less
than the maximum DRAM RAS assert time t_RAS when the refresh cycle is longer than the t_RAS
maximum.
When an external circuit is added to keep the CASHH, CASHL, CASLH, and CASLL signals
connected to the DRAM asserted only when the CS3 level is low, there are no restrictions on the
use of RAS down mode.
CKIO
A26–A14
A13–A0
Read
RAS
CASn
RD/WR
RD
D31–D0
Write
RD/WR
RD
D31–D0
CS3
BS
Tp
Tr Tc1 Tc2
Figure 7.34 Burst Access Timing
Tc1 Tc2
187