SH7604 Datasheet, PDF (139/633 Pages) Hitachi Semiconductor – Hardware Manual

6.3.6 Example of Use
Break on a CPU Instruction Fetch Bus Cycle:
A. Register settings: BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054
BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1400
Conditions set (channel A/channel B independent mode):
Channel A:
Address = H'00000404, address mask H'00000000
Bus cycle = CPU, instruction fetch (after execution), read
(operand size not included in conditions)
Channel B:
Address = H'00008010, address mask H'00000006
Data H'00000000, data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read
(operand size not included in conditions)
A user break will occur after the instruction at address H'00000404 is executed, or a user break
will be generated before the execution of the instruction at address H'00008010–H'00008016.
B. Register settings: BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056
BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1010
Conditions set (channel A → channel B sequential mode):
Channel A:
Address = H'00037226, address mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read, word
Channel B:
Address = H'0003722E, address mask H'00000000
Data H'00000000, data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read, word
The instruction at address H'00037226 will be executed and then a user break interrupt will occur
before the instruction at address H'0003722E is executed.
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