SH7604 Datasheet, PDF (234/633 Pages) Hitachi Semiconductor – Hardware Manual

CPU
pipeline
stage
Cache
address
bus
Cache
data bus
Internal
address
bus
Internal
data bus
EX
MA
EX
Address A
Address B
Cache tag comparison
Data array write
WB
MA
Cache tag comparison
Address A
Address A + 4 Address A + 8 Address A + 12 Address A
Address A + 4 Address A + 8 Address A + 12 Address A
EX: Instruction execution
MA: Memory access
WB: Write-back
Figure 8.4 Read Access in Case of a Cache Miss
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