SH7604 Datasheet, PDF (629/633 Pages) Hitachi Semiconductor – Hardware Manual

Cache
Cache control register (CCR)
H'FFFFFE92
8
Bit
Item
7
6
5
4
3
2
1
0
Bit Name
W1
W0
—
CP
TW
OD
ID
CE
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Value
Description
7, 6 Way specification
0 0 Way 0 (Initial value)
(W1, W0)
0 1 Way 1
1 0 Way 2
1 1 Way 3
4 Cache purge (CP)
0 Normal operation (Initial value)
1 Cache purge
3 Two-way mode (TW)
0 Four-way mode (Initial value)
1 Two-way mode
2 Data replacement
0 Normal operation (Initial value)
disable (OD)
1 Data not replaced even when cache miss occurs in data
access
1 Instruction replacement 0 Normal operation (Initial value)
disable (ID)
1 Data not replaced even when cache miss occurs in
instruction fetch
0 Cache enable (CE)
0 Cache disabled (Initial value)
1 Cache enabled
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