SH7604 Datasheet, PDF (67/633 Pages) Hitachi Semiconductor – Hardware Manual

3.2.2 Clock Operating Mode Settings
Table 3.2 lists the functions and operation of clock modes 0 to 6.
Note that TBP-176 package products can only be used in clock modes 4 to 6.
Table 3.2 Operating Modes
Clock Mode
0
1
2
3
4
5
6
Function/Operation
Clock Source
PLL circuits 1 and 2 operate. A clock with the same phase as Crystal resonator/
the internal chip clock is output from the CKIO pin.
External clock input
PLL circuits 1 and 2 operate. A clock shifted 90° from the
CKIO pin output is supplied to the internal chip clock.
Crystal resonator/
External clock input
Only PLL circuit 2 operates. The clock from PLL circuit 2 is
output from the CKIO pin. Phases are not matched in this
mode.
Crystal resonator/
External clock input
Only PLL circuit 2 operates. The CKIO pin is high impedance. Crystal resonator/
Phases are not matched in this mode.
External clock input
Set this mode when the CKIO pin inputs a clock having a
frequency equivalent to the object operating frequency and
PLL circuit 1 synchronizes the phases of the input clock and
the internal clock.
External clock input
Set this mode when the CKIO pin inputs a clock having a
frequency equivalent to the object operating frequency and
PLL circuit 1 shifts the phases of the input clock and internal
clock by 90 degrees.
External clock input
Set this mode when a clock having a frequency equivalent to External clock input
that of clocks input from the CKIO pin are used. PLL circuits 1
and 2 do not operate.
When clock modes 0 to 3 are selected, the input frequency or its double or quadruple (produced by
PLL circuit 2) is used as the internal clock. When clock modes 4 to 6 are selected, the clock pause
function can modify the frequency of clocks input from the CKIO pin or can stop the sending of
clock signals (see section 14.4, Standby Mode). When clock modes 4 to 6 are set, PLL circuit 2
stops.
Table 3.3 lists the relationship between pins MD2 to MD0 and the clock operating mode. Do not
switch the MD2–MD0 pins while they are operating. Switching will cause operating errors.
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