SH7604 Datasheet, PDF (22/633 Pages) Hitachi Semiconductor – Hardware Manual

1.2 Block Diagram
Figure 1.1 shows a block diagram of the SH7604.
MULT
Cache
address array
Cache
controller
CPU
Exception
handling
interrupt
controller
Cache
data
array
User break
controller
DIVU
Vector address
Direct
memory
access
controller
(× 2 channels)
External bus
interface
Bus state
controller
Clock pulse
generator
Figure 1.1 Block Diagram
6
16-bit free
running
timer
Serial
communi-
cation
interface
Watchdog
timer
Operating-
mode
controller