SH7604 Datasheet, PDF (244/633 Pages) Hitachi Semiconductor – Hardware Manual

rewrite is detected, data coherency can be maintained. When data that extends over multiple
words, such as a structure, is rewritten, however, interrupts are generated at the rewrites, which
can lower performance. This method is most appropriate for cases in which it is difficult to predict
and detect the timing of data updates and the update frequency is low.
To purge the cache using program logic, the data updates are detected by the program flow and the
cache is then purged. For example, if the program inputs data from a disk, whenever reading of a
unit (such as a sector) is completed, the buffer address used for reading or the entire cache is
purged, thereby maintaining coherency. When data is to be handled between two processors, only
flags to provide mutual notification of completion of data preparation or completion of a fetch are
placed in the cache-through area. The data actually transferred is placed in the cache area and the
cache is purged before the first data read to maintain the coherency of the data. When semaphores
are used as the means of communication, data coherency can be maintained even when the cache
is not purged by utilizing the TAS instruction. The TAS instruction is not read within the cache;
the external access is always direct. This means that data can be synchronized with other masters
when it is read.
When the update unit it is small, specific addresses can be purged, so only the relevant addresses
are purged. When the update unit is larger, it is faster to purge the entire cache rather than purging
all the addresses in order, and then read in the data previously existing in the cache again from
external memory.
8.5.4 Two-Way Cache Mode
The 4-kbyte cache can be used as 2-kbyte RAM and 2-kbyte mixed instruction/data cache memory
by setting the TW bit in CCR to 1. Ways 2 and 3 become cache, and ways 0 and 1 become RAM.
The cache and RAM are initialized by setting the CP bit in CCR to 1. The valid bit and LRU bits
are cleared to 0.
When the initial values of the LRU information are set to 0, ways 3 and 2 are initially used, in that
order. Ways 3 and 2 are subsequently selected for replacement as specified by the LRU
information. The conditions for updating the LRU information are the same as for four-way mode,
except that the number of ways is two.
When designated as 2-kbyte RAM, ways 0 and 1 are accessed by data array access. Figure 8.14
shows the address mapping.
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