SH7604 Datasheet, PDF (614/633 Pages) Hitachi Semiconductor – Hardware Manual

UBC
Break data register BL (BDRBL) H'FFFFFF72
16/32
Item
Bit Name
Initial Value
R/W
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000 0000 0000 0000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 Break data BDB15–BDB0
Description
These bits specify the lower bits (bit 15 to bit 0) of the
channel B break condition data
Break data mask register BH
(BDMRBH)
H'FFFFFF74
16/32
Item
Bit Name
Initial Value
R/W
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM BDM
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16
0000 0000 0000 0000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 Break data mask
BDMB31–BDMB16
Value
Description
0 Channel B break address BDBn is included in the break
conditions (Initial value)
1 Channel B break address BDBn is masked and therefore
not included in the break conditions
n = 31 to 16
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