SH7604 Datasheet, PDF (209/633 Pages) Hitachi Semiconductor – Hardware Manual

7.7.3 Wait State Control
When the clock frequency is raised, 1 cycle may not always be sufficient for all states to end, as in
basic access. Setting bits in WCR and MCR enables the state to be lengthened. Figure 7.39 shows
an example of lengthening a state using settings. The Tp cycle that ensures a sufficient CE
precharge time can be extended to 2 cycles by insertion of a Tpw cycle by means of the TRP bit in
MCR. The number of cycles between BS assert and the end of access can be extended from 2 to 4
cycles by setting the W31/W30 bits in WCR. When a value other than 00 is set in W31 and W30,
the external wait pin WAIT is also sampled, so the number of cycles can be further increased.
Figure 7.40 shows the timing of wait state control using the WAIT pin. In either case, when
consecutive accesses occur, the Tp cycle of one access overlaps the Tc2 cycle of the previous
access. The RCD bit in MCR is set to 0 for a pseudo-SRAM interface, but when set to 1, the
number of cycles from the CE assert to the BS assert or write data output becomes 2.
Tp
Tpw
Tr
Tc1
Tw
Tc2
CKIO
A26–A1
CS3
BS
CE
OE
Read
RD
WEn
D31–D0
OE
Write
RD
WEn
D31–D0
Figure 7.39 Wait State Timing
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