SH7604 Datasheet, PDF (285/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: Byte, word, longword
Transfer bus mode: Cycle-steal mode
Transfer address modes: Dual and single modes
DREQ detection method: Edge detection
DACK output timing: Read, write (dual), DMAC cycle (single)
Bus cycle: Basic bus cycle
Clock
*¹
DREQ
1st acceptance
DACK
*¹
2nd acceptance
2 cycles
Bus
cycle
CPU
CPU
*²
DMAC
Notes: 1. Request detection
2. When DACK is output in a write (dual), the cycle is a DMAC read. Otherwise, the cycle
is a CPU cycle.
Figure 9.35 DREQ Pin Input Detection Timing in Cycle-Steal Mode with Edge
Detection (1)
Figures 9.36 and 9.37 show examples of how to change the bus width of an external device.
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