SH7604 Datasheet, PDF (204/633 Pages) Hitachi Semiconductor – Hardware Manual

7.6.6 Refresh Timing
The BSC has a function for controlling DRAM refreshes. By setting the MCR’s RMODE bit to 0
and RFSH bit to 1, distributed refreshing using the CAS-before-RAS refresh cycle can be
performed.
Refreshes are performed at the interval determined by the input clock selected with CKS2–CKS0
in RTCSR and the value set in RTCOR. Set the values of RTCOR and CKS2–CKS0 so they
satisfy the refresh interval specifications of the DRAM being used. First, set RTCOR, RTCNT and
the RMODE and RFSH bits in MCR, then set the CKS2–CKS0 bits. When a clock is selected with
the CKS2–CKS0 bits, RTCNT starts counting up from the value at that time. The RTCNT value is
constantly compared to the RTCOR value and a request for a refresh is made when the two match,
starting a CAS-before-RAS refresh. RTCNT is cleared to 0 at that time and the count up starts
again. Figure 7.35 shows the timing for the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by the TRAS bit in MCR. As
with ordinary accesses, the specification of the RAS precharge time in refresh cycles follows the
setting of the TRP bit in MCR.
Tp
Trr
Trc1
Trc2
Tre
CKIO
RAS
CASn
RD/WR
RD
CS3
BS
Figure 7.35 Refresh Cycle Timing
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