SH7604 Datasheet, PDF (510/633 Pages) Hitachi Semiconductor – Hardware Manual

Table 16.7
Bus Timing With PLL On and 1/4 Cycle Delay [Mode 1, 5]
(Conditions: V_CC = 3.0 to 5.5 V, Ta = –20 to +75°C)
Item
Address delay time
BS delay time
CS delay time 1
CS delay time 2
Read/write delay time
Read strobe delay time 1
Read data setup time 1
Read data setup time 3
(SDRAM)
Read data hold time 2
Read data hold time 4
(SDRAM)
Read data hold time 5
(DRAM)
Read data hold time 6
(PSRAM)
Read data hold time 7
(interrupt vector)
Write enable delay time
Write data delay time 1
Write data hold time 1
Data buffer on time
Data buffer off time
Symbol
t_AD
t_BSD
t_CSD1
t_CSD2
t_RWD
t_RSD1
t_RDS1
t_RDS3
Min
Max
Unit Figures
—
1/4 tcyc + 28 ns 16.14, 16.20, 16.40,
16.52, 16.66, 16.68
—
1/4 tcyc + 25 ns 16.14, 16.20, 16.40,
16.52, 16.66
—
1/4 tcyc + 25 ns 16.14, 16.20, 16.40,
16.52, 16.66
—
3/4 tcyc + 25 ns 16.14, 16.66
—
1/4 tcyc + 25 ns 16.14, 16.20, 16.40,
16.52, 16.66
—
3/4 tcyc + 25 ns 16.14, 16.40, 16.52,
16.66, 16.68
1/4 tcyc + 10 —
ns 16.14, 16.40, 16.52,
16.66, 16.68
1/4 tcyc + 10 —
ns 16.20
t_RDH2
0
t_RDH4
0
—
ns 16.14, 16.66
—
ns 16.20
t_RDH5
0
—
ns 16.40
t_RDH6
0
—
ns 16.52
t_RDH7
0
—
ns 16.68
t_WED1
t_WDD
t_WDH1
t_DON
t_DOF
3/4 tcyc + 3 3/4 tcyc + 25 ns
—
1/4 tcyc + 25 ns
1/4 tcyc + 3 —
ns
—
1/4 tcyc + 25 ns
—
1/4 tcyc + 25 ns
16.14, 16.15, 16.52,
16.53
16.15, 16.27, 16.41,
16.53
16.15, 16.27, 16.41,
16.53
16.15, 16.27, 16.41,
16.53
16.15, 16.27, 16.41,
16.53
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