SH7604 Datasheet, PDF (276/633 Pages) Hitachi Semiconductor – Hardware Manual

Clock
DACK
Address
bus
CPU H
Invalid
*1
*2 write
DMAC read H DMAC read L
DMAC write
Notes: 1. L: LSB side
2. H: MSB side
Basic timing
Figure 9.16 DACK Output in Ordinary Space Accesses
(AM = 0, Longword Access to 16-Bit External Device)
Clock
DACK
Address
bus
CPU H
DMAC
read HH
DMAC
read HL
DMAC
read LH
DMAC
read LL
Basic timing
Figure 9.17 DACK Output in Ordinary Space Accesses
(AM = 0, Longword Access to 8-Bit External Device)
Clock
DACK
Address
bus
CPU H
Invalid
write
DMAC read H DMAC read L
DMAC write
Basic timing
Figure 9.18 DACK Output in Ordinary Space Accesses
(AM = 0, Word Access to 8-Bit External Device)
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