SH7604 Datasheet, PDF (120/633 Pages) Hitachi Semiconductor – Hardware Manual

Interrupt clear instruction
ex. mov r0,@r1
Synchronization instruction
ex. mov @r1,r0
Next interrupt can
Writing complete
be accepted
F D EM
F D EM
1 cycle
External write
Min. 2 cycles
External read
W _{Min. 2 cycles}
RTE instruction
Delay slot instruction
Instruction at destination
of return from interrupt
FD
F
E MM
DE
FDE
5 cycles
IRL3–IRL0
Figure 5.11 Pipeline Operation in Return with RTE
Interrupt clear instruction
ex. mov r0,@r1
Synchronization instruction
ex. mov @r1,r0
Next interrupt can
Writing complete
be accepted
F D EM
F D EM
External write
Min. 2 cycles
External read
W _{Min. 2 cycles}
4 cycles
LDC instruction
FDE
Interrupt-disable instruction
FDE
Ordinary instruction
FDE
5 cycles
IRL3–IRL0
Figure 5.12 Pipeline Operation when Interrupts are Enabled by Modifying SR
104