SH7604 Datasheet, PDF (595/633 Pages) Hitachi Semiconductor – Hardware Manual

FRT
Timer interrupt enable register
(TIER)
H'FFFFFE10
8
Bit
Item
7
6
5
4
3
2
1
0
Name
ICIE
—
—
—
OCIAE OCIBE OVIE
—
Initial Value
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Value
Description
7 Input capture interrupt 0 Disables interrupt requests (ICI) from ICF (Initial value)
enable (ICIE)
1 Enables interrupt requests (ICI) from the ICF
3 Output compare
0 Disables interrupt requests (OCIA) from OCFA
interrupt A enable
(Initial value)
(OCIAE)
1 Enables interrupt requests (OCIA) from OCFA
2 Output compare
0 Disables interrupt requests (OCIB) from OCFB
interrupt B enable
(Initial value)
(OCIBE)
1 Enables interrupt requests (OCIB) from OCFB
1 Timer overflow interrupt 0 Disables interrupt requests (OVI) from OVF (Initial value)
enable (OVIE)
1 Enables interrupt requests (OVI) from OVF
Free-running timer control/status
register (FTCSR)
H'FFFFFE11
8
Bit
Item
7
6
5
4
3
2
1
Bit Name
ICF
—
—
—
OCFA OCFB OVF
Initial Value
0
0
0
0
0
0
0
R/W
R/(W)*
—
—
—
R/(W)* R/(W)* R/(W)*
Note: For bits 7, and 3 to 1, the only value that can be written is 0 (to clear the flags)
0
CCLRA
0
R/W
Bit
Bit Name
Value
Description
7 Input capture flag (ICF) 0 Clear conditions: When ICF = 1, ICF is read and then 0 is
written to it (Initial value)
1 Set conditions: When FRC value is sent to ICR by the
input capture signal
3 Output compare flag A 0 Clear conditions: When OCFA = 1, OCFA is read and
(OCFA)
then 0 is written to it (Initial value)
1 Set conditions: When FRC value becomes equal to
OCRA
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