SH7604 Datasheet, PDF (197/633 Pages) Hitachi Semiconductor – Hardware Manual

c. No PLL Used
External
CLK (CKIO)
Internal
CLK
Clock circut delay α (fluctuates with temperature and voltage)
1 – α cycle
Signal
output
SDRAM input latch
1/2 + α cycle
SDRAM
data output
Input
data latch
Figure 7.28 Phase Shift by PLL (cont)
7.6 DRAM Interface
7.6.1 DRAM Direct Connection
When the DRAM and other memory enable bits (DRAM2–DRAM0) in BCR1 are set to 010, the
CS3 space becomes DRAM space, and a DRAM interface function can be used to directly connect
the SH7604 to DRAM.
The data width of an interface can be 16 or 32 bits (figures 7.29 and 7.30). Two-CAS 16-bit
DRAMs can be connected, since CAS is used to control byte access. The RAS, CASHH, CASHL,
CASLH, CASLL, and RD/WR signals are used to connect the DRAM. When the data width is 16
bits, CASHH, and CASHL are not used. In addition to ordinary read and write access, burst access
using high-speed page mode is also supported.
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