SH7604 Datasheet, PDF (165/633 Pages) Hitachi Semiconductor – Hardware Manual

Instruction fetches are always performed in 32-bit units. When branching to an odd word
boundary (4n + 2 address), instruction fetches are performed in longword units from a 4n address.
Figures 7.2 to 7.4 show the relationship between device data widths and access units.
A26–A0 ^D31
000000 7
000001
000002
000003
000000 15
000002
000000 31
D23
0
7
87
24 23
D15
0
7
0
15
16 15
D7
0
7
87
87
D0 _{32-bit device data input/output pin}
Byte read/write of address 0
Byte read/write of address 1
Byte read/write of address 2
0 Byte read/write of address 3
Word read/write of address 0
0 Word read/write of address 2
0 Longword read/write of address 0
Figure 7.2 32-Bit External Devices and Their Access Units (Ordinary)
A26–A0 ^D15
000000 7
000001
000002 7
000003
000000 15
000002 15
000000 31
000002 15
D7
0
7
0
7
D0 _{16-bit device data input/output pin}
Byte read/write of address 0
0 Byte read/write of address 1
Byte read/write of address 2
0 Byte read/write of address 3
0 Word read/write of address 0
0 Word read/write of address 2
16
0 Longword read/write of address 0
Figure 7.3 16-Bit External Devices and Their Access Units (Ordinary)
A26–A0 ^D7
000000 7
000001 7
000002 7
000003 7
000000 15
000001 7
000002 15
000003 7
000000 31
000001 23
000002 15
000003 7
D0 _{8-bit device data input/output pin}
0 Byte read/write of address 0
0 Byte read/write of address 1
0 Byte read/write of address 2
0 Byte read/write of address 3
8
0 Word read/write of address 0
8
0 Word read/write of address 2
24
26
8
0 Longword read/write of address 0
Figure 7.4 8-Bit External Devices and Their Access Units (Ordinary)
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